Flip Flop Truth Tables

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Every flip-flop in the library — D, T, JK and RS — clocked side by side while a two-bit stimulus walks their inputs through the complete truth table.

One shared stimulus, four flip-flops. Three Clock blocks publish CLK, A and B on named Go-To tags; From tags pick them back up at each flip-flop, so nothing is wired across the sheet. Each Q is republished on its own tag and read by a single six-row Plot.

How the sweep works

The stimulus is three ordinary Clock blocks running at related rates — no special pattern-generator part required. CLK ticks at 100 Hz, so a rising edge lands every 10 ms. B runs at a quarter of that rate and A at an eighth, which makes the pair (A, B) a two-bit binary counter stepping 00 → 01 → 10 → 11 and holding each row for two clock edges before advancing. One full sweep is 80 ms; the run covers two of them.

All three clocks use phase = 0.5, and that is the load-bearing detail. A and B change state at 20, 40, 60 and 80 ms while CLK rises at 5, 15, 25 ms and so on — every clock edge lands exactly halfway between two input transitions, 5 ms of margin on either side. Line the inputs up with the clock instead and you get a setup race where the flip-flop's answer depends on which block the scheduler happens to run first.

A also drives T, and B also drives D, so the two single-input flip-flops cover their own (two-row) tables inside the same sweep.

The tables

The JK and RS flip-flops see the same input pair and agree on three of the four rows. The fourth is the whole reason both parts exist:

A (S / J)	B (R / K)	JK-FF	RS-FF
0	0	hold	hold
0	1	reset, Q := 0	reset, Q := 0
1	0	set, Q := 1	set, Q := 1
1	1	toggle	hold (invalid input)

S = R = 1 is the forbidden input of a classic RS latch. NumaSim's model defines it as a hold, so the result is deterministic rather than a race — it does not toggle. On the plot, Q_JK and Q_RS sit on top of each other for the first three-quarters of every sweep and then split apart at t = 65 ms.

The two single-input parts:

Input	D-FF (D = B)	T-FF (T = A)
0	Q := 0	hold
1	Q := 1	toggle

The T, JK and RS flip-flops all start from q0 = 1. Starting from zero would make the first hold row indistinguishable from a reset — Q would sit at 0 either way and prove nothing.

What to read off the plot

The Plot is a six-row logic-analyzer stack sharing one X axis: CLK, then A and B together, then each Q. Zooming one row zooms all of them, so you can drop the cursor on a clock edge and read every flip-flop's answer down the column.

• Q_D never moves between edges. It changes 5 ms after B does, because that is when the next rising edge arrives. This is the whole point of edge-triggering: the flip-flop samples its input at one instant and ignores it the rest of the time.
• Q_T holds flat for the first half of each sweep (A = 0), then becomes a clean square wave at half the clock rate once A goes high. A T flip-flop with its input tied high is a divide-by-two counter.
• Q_JK and Q_RS diverge only in the last quarter. From 65 ms the JK alternates on every edge while the RS holds at 1.
• The second sweep, from 80 ms on, is an exact repeat of the first — worth checking, because it proves the sequence is a genuine steady-state cycle and not an artifact of the initial conditions.

Things to try

Enable the Reset port parameter on any flip-flop and wire a From tag into the new rst pin: a synchronous active-high clear that beats S, R, J, K, D and T on the rising edge. Swap A and B on the JK to watch the set and reset rows trade places. Or change q0 on the RS from 1 to 0 and confirm the 1 1 row still refuses to toggle — it holds whatever it was holding, which is exactly what makes it safe.