Chapter 4 — Sources and control signals

Module 1 built the whole per-step engine for smooth, linear elements — resistors, inductors, capacitors — driven by an idealized source. Real power systems are more demanding in two ways. First, sources have waveforms (DC, AC, Harmonics, a soft-start ramp) and impedance (they are not infinitely stiff). Second, almost nothing runs open-loop: a controller senses a quantity, computes, and commands a device. This chapter covers both — how a source enters the time-domain solve, and how the control domain is solved alongside the electrical network — and ends by tracing a control signal all the way to the gate of a switch. That last step is the doorway to the switching devices of Chapters 5-7.

Learning objectives

By the end of this chapter you should be able to:

• Write the time-domain expression for a DC and an AC source.
• Add a source's series (Thévenin) impedance and predict the terminal-voltage sag under load.
• Explain why a soft-start ramp avoids startup transient.
• Describe how control blocks (gain, adder, integrator, transfer function) are discretized and solved each step, alongside the electrical network.
• Explain why the control blocks are evaluated in a topological order, and what a feedback loop needs in order to have one.
• Trace a control signal from a sensed quantity to a device command in a real closed loop.

4.1 Independent sources in the time domain

An independent source imposes a known waveform regardless of the rest of the circuit. The two you will meet constantly:

• DC source: a constant, $v(t)=V$. Every sample in Module 1 used one.
• AC source: a sinusoid,$$v(t)=V_{\text{pk}}\sin (2\pi ft+\phi ),$$set by an amplitude, a frequency $f$, and a phase $\phi$.

In power systems it is customnary to specify the RMS value of the source. A sinusoid's RMS and peak are related by

$$V_{\text{pk}}=\sqrt{2}{V}_{\text{rms}}.$$

So a source you set to "$10\text{V}$, $60\text{Hz}$" actually swings to a peak of $10\sqrt{2}\approx 14.14\text{V}$.

Recall from Chapter 3 that an ideal voltage source does not have a Norton equivalent and thus cannot be simulated using classical nodal analysis; NumaSim overcomes this limitation using modified nodal analysis, adding the source branch current as an extra unknown and a constraint row.

4.2 Source impedance (the Thévenin view)

A truly ideal source holds its voltage no matter how much current it delivers. Real sources cannot: a generator, a wall outlet, or the grid behind a bus all have internal impedance. The standard model is a Thévenin equivalent — an ideal source in series with an impedance $Z_s$ (a resistance $R_s$, often with a series inductance $L_s$).

A source as a Thévenin equivalent: an ideal source $V$ behind a series impedance $R_s$ (optionally $L_s$). Under load current $i$ the accessible terminal voltage sags to $v_{\mathrm{term}}=V-i{R}_s$.

Under a load drawing current $i$, the accessible terminal voltage is

$$v_{\text{term}}(t)=V-i(t)R_s.$$

The stiffer the source (smaller $R_s$), the less it sags. NumaSim's voltage source exposes a series_resistance (and optional l_main) for exactly this; the power-electronics samples set it very small (milliohms) so the source is nearly ideal, but the same knob is what lets a source represent a weak grid or sets the available fault current (a theme we return to in Module 6).

4.3 Ramps and soft-starts

Energizing a circuit with a hard step at $t=0$ injects the network's fastest possible transient — precisely the ringing and inrush you saw in Module 1. Sometimes that is the study. But often you only want the circuit's operating point, and a startup surge just pollutes the early waveform (or saturates a machine, or trips a limiter). The fix is a soft-start: ramp the source amplitude from zero up to its final value over a short ramp_time instead of stepping it:

$$v(t)=\{\begin{array}{ll}{\displaystyle \frac{t}{t_{\text{ramp}}}}{V}_{\text{pk}}\sin (2\pi ft+\phi ),& t<t_{\text{ramp}},\\ V_{\text{pk}}\sin (2\pi ft+\phi ),& t\ge t_{\text{ramp}}.\end{array}$$

Ramping over several cycles lets the inductors and capacitors charge gently, so the circuit slides into its steady state instead of lurching into it. This is why several NumaSim samples specify a non-zero ramp_time.

4.4 The control domain

Everything so far lives in the electrical network — nodes, branches, and Kirchhoff's current law. NumaSim solves a second world in lock-step: the control domain, a signal-flow graph of blocks wired output-to-input. These are not electrical nodes; a control wire carries a single scalar value in one direction, not a voltage/current pair obeying KCL. Typical blocks:

Block	Does	Example NumaSim type
Constant	emits a fixed value (a setpoint)	const_dbl
Gain	multiplies by $K$	gain
Adder	adds/subtracts inputs	add2
Integrator	accumulates $\int udt$	integrator
Transfer function	a filter / lag $H(s)$	tf1
PID	proportional-integral-derivative control	pid
Multiply	products of two signals	multiply
PWM	turns a duty command into a gate pulse train	pwm

Continuous blocks are discretized exactly the way Chapter 2 discretized an inductor — with the trapezoidal rule. Take a first-order lag $H(s)=K/(1+sT)$, i.e. the ODE $T\dot{y}+y=Ku$. Apply the trapezoidal rule over one step:

$$T(y_n-y_{n-1})+\frac{\mathrm{\Delta }t}{2}(y_n+y_{n-1})=K\frac{\mathrm{\Delta }t}{2}(u_n+u_{n-1}),$$

which rearranges to the ready-to-run difference equation

$$\boxed{{\displaystyle y_n=\frac{(T-\frac{\mathrm{\Delta }t}{2})y_{n-1}+K\frac{\mathrm{\Delta }t}{2}(u_n+u_{n-1})}{T+\frac{\mathrm{\Delta }t}{2}}}}.$$

Just like the companion models, everything on the right is either the present input or a value carried from the previous step. Each control block updates its state once per step, and its output either feeds another control block or commands an electrical device. Because control signals are named, they are observables you can plot on the scope like any voltage — see Observables.

Evaluation order is a topological sort

Unlike the electrical network, the control domain is never assembled into a matrix and solved simultaneously. Each block is a plain assignment, $y_n=f(\text{inputs},\text{state})$, so the only thing left for the engine to get right is the order in which the blocks are evaluated. Run a adder before the gain that feeds it, and the adder adds a stale value.

Read the control domain as a directed graph: one vertex per block, and an edge from each block that produces a signal to each block that consumes it. "Every producer runs before its consumers" is then exactly a topological sort of that graph — a linear ordering of the vertices in which, for every edge $u\to v$, $u$ appears before $v$. NumaSim builds it with the textbook in-degree method (Kahn's algorithm): repeatedly emit any block whose inputs have all been produced, then delete its outgoing edges. The cost is linear in the number of blocks plus wires. For the loop of §4.5, one valid answer is

multiply $\to$ tf1 $\to$ add2 $\to$ pid $\to$ pwm,

with the const_dbl setpoint emitted anywhere before the adder. That freedom is normal — a graph usually admits many topological orders — and every valid order produces identical numbers, since each block reads only inputs that are already final for the step.

Two properties are worth internalizing.

The sort happens once, not every step. The order is computed when the circuit is compiled, before $t=0$; each step then walks the same fixed schedule. It is the control-domain twin of factorizing $\mathbf{G}$ once (Chapter 3): do the structural work at setup so the inner loop is pure arithmetic.

Feedback needs a delay somewhere. A topological order exists only for an acyclic graph, and a closed loop is a cycle by definition. Two cases:

• The loop closes through the network. Signals crossing between the control and electrical domains carry the previous step's value: the IGBT of §4.5 acts on the gate computed one step earlier, and the controller sees measurements from one step earlier. That built-in delay cuts the cycle before the sort ever sees it, which is why the loop of §4.5 sorts cleanly with no extra work from you.
• The loop stays inside the control domain — a block's output reaching its own input through control blocks only. That is a real cycle, the classic algebraic loop: the block would need its own output in order to compute its own output. Break it with an explicit unit delay (unit_delay, the $z^{-1}$ block), whose output is its input from the previous step and so imposes no ordering constraint. Leave the cycle unbroken and the run still proceeds — the engine cuts the loop itself, treats the cut edge as one-step-delayed, and says so in the log panel — but then where the delay lands is the tie-break's choice, not yours.

4.5 From a control signal to a device command

The payoff of the control domain is closing a loop: sense an electrical quantity, compute a correction, and command a device. The PWM power control sample is a compact, complete example. Its job is to hold the average power delivered to a resistive load at a setpoint, by modulating an IGBT.

The closed loop in the PWM-power-control sample. A constant $P_{\mathrm{ref}}=30$ is compared with the measured average power $P_{\mathrm{avg}}$; the error drives a PI controller whose output is the PWM duty; the PWM gates the IGBT feeding the load. The sensed load voltage and current are multiplied to instantaneous power and low-pass filtered back to $P_{\mathrm{avg}}$.

Follow the signals (every name below is a real observable in the file):

1. A const_dbl emits the setpoint P_ref $=30$.
2. A adder (add2) forms the error $=P_{\text{ref}}-P_{\text{avg}}$.
3. A pid (here a PI) turns the error into a duty command in $[0,1]$.
4. A pwm block converts the duty into a gate pulse train.
5. The gate drives the IGBT, an electrical switch, which chops the $50\text{V}$ bus into the load.
6. Sensing closes the loop: the load voltage V_R and current I_R are multiply-ed into instantaneous power P_inst, then a first-order transfer function (tf1) averages out the switching ripple to P_avg, which returns to the adder.

The control signal gate is the hinge: it is computed in the control domain but consumed by an electrical device. How that IGBT — and diodes and thyristors — turn a gate or a terminal voltage into a change in the network is the whole of Chapter 5.

4.6 Lab: sources and a control loop

Lab 4A — read an AC source and confirm the RMS/peak factor

Open the half-wave rectifier in app →

(Full description: half-wave rectifier.)

Run it and look at Vac, the source waveform:

• Its peak is about $14.14\text{V}$, not $10\text{V}$ — because the source is rated $10\text{V}$ RMS and $10\sqrt{2}=14.14$.
• Its period is $1/60\approx 16.7\text{ms}$.

(We will study the rectified output Vdc in Chapter 7; for now just confirm the input.)

Lab 4B — watch a control loop acquire its setpoint

Open the PWM power controller in app →

(Full description: PWM power control.)

Run it and plot error and P_avg. The controller starts off-setpoint, and over the run the PI drives error toward zero while P_avg climbs to and holds the setpoint of $30$. Identify each block from §4.5 on the canvas, and note which wires are control (thin, one-way, carrying error, duty, P_avg) versus electrical (carrying the $50\text{V}$ bus into the load).

4.7 Summary

• A DC source is a constant; an AC source is $V_{\text{pk}}\sin (2\pi ft+\phi )$, and NumaSim rates AC amplitude in RMS, so the peak is $\sqrt{2}$ times the rating.
• Real sources carry a Thévenin series impedance; the terminal voltage sags as $v_{\text{term}}=V-i{R}_s$ under load.
• A soft-start ramp eases the network into its operating point instead of hitting it with an artificial step.
• The control domain is a signal-flow graph solved alongside the network; continuous blocks are discretized with the same trapezoidal rule used for R, L, C, giving one difference equation per block.
• Those blocks are evaluated in a topological order of the signal-flow graph, computed once at compile time so every producer runs before its consumers. A loop closing through the network is cut by the one-step cross-domain delay; a loop confined to the control domain needs an explicit $z^{-1}$ unit delay.
• Closing a loop means sensing an electrical quantity, computing in the control domain, and commanding a device — the gate signal that drives a switch is the bridge into Chapter 5.

4.8 Problems

Problem 4.1. A NumaSim AC source is set to $230\text{V}$, $50\text{Hz}$. What is its peak voltage, and what is its period?

Solution 4.1

The rating is RMS, so the peak is $V_{\text{pk}}=\sqrt{2}(230)\approx 325.3\text{V}$. The period is $T=1/f=1/50=20\text{ms}$.

Problem 4.2. A Thévenin source has open-circuit voltage $100\text{V}$ and series resistance $R_s=2\mathrm{\Omega }$. It feeds a $18\mathrm{\Omega }$ resistive load. Find the load current and the terminal voltage.

Solution 4.2

The current is $i=V/(R_s+R_L)=100/(2+18)=5\text{A}$. The terminal voltage is $v_{\text{term}}=V-i{R}_s=100-5(2)=90\text{V}$ (equally, $i{R}_L=5(18)=90\text{V}$). The $10\text{V}$ lost across $R_s$ is the source's internal sag.

Problem 4.3. Why might you ramp a source up over several cycles rather than applying it as a step, even when you ultimately want the steady state?

Solution 4.3

A hard step excites the circuit's full transient (inrush, ringing) that then has to decay before the steady state is visible — and it can drive nonlinear elements (saturating transformers, limiter-equipped controllers) into large excursions. Ramping the amplitude lets the inductors and capacitors charge gradually, so the circuit slides into its operating point with little or no surge, giving a clean steady state sooner.

Problem 4.4. In the PWM-power-control loop, list the signal path from the sensed load quantities to the IGBT gate, and classify each block as control- or electrical-domain.

Solution 4.4

Sensed V_R and I_R (electrical measurements) $\to$ multiply $\to$P_inst $\to$ first-order tf1 filter $\to$ P_avg $\to$ adder (add2, subtracting from P_ref) $\to$ error $\to$ pid (PI) $\to$ duty $\to$pwm $\to$ gate. Every block from multiply through pwm is in the control domain; the IGBT and the load it feeds are electrical. The gate signal is the control-to-electrical hand-off.

Problem 4.5. The instantaneous power P_inst is low-pass filtered to P_avg before being compared with the setpoint. Why not feed P_inst directly to the adder?

Solution 4.5

P_inst is the product of a switched voltage and current, so it is full of switching-frequency ripple. Feeding that raw into the controller would make the PI chase the ripple, not the average. The loop's job is to regulate average delivered power, so a first-order filter extracts the slow average P_avg and the controller acts on that. (This is the same reason a rectifier needs a reservoir capacitor — Chapter 7.)

Problem 4.6. Four control blocks are wired $A\to C$, $B\to C$, $C\to D$, and $B\to D$. In what order or orders may the engine evaluate them? Now add a wire $D\to B$. What changes?

Solution 4.6

$A$ and $B$ have no inputs, so either may go first; $C$ needs $A$ and $B$; $D$ needs $B$ and $C$. Exactly two topological orders satisfy that: $A,B,C,D$ and $B,A,C,D$. Both give the same numbers.

Adding $D\to B$ creates the cycle $B\to D\to B$ (and $B\to C\to D\to B$), so the graph is no longer acyclic and no topological order exists. If the loop lies entirely in the control domain, insert a unit_delay on the $D\to B$ path: $B$ then reads $D$'s previous-step output, the edge stops constraining the order, and $A,B,C,D$ is valid again. Without the explicit delay the engine breaks the cycle itself and warns you.

4.9 References

• H. W. Dommel, Electromagnetic Transients Program (EMTP) Theory Book, Bonneville Power Administration — sources and the transient analysis of control systems.
• P. Kundur, Power System Stability and Control, McGraw-Hill — modeling of control blocks and transfer functions.
• J. Arrillaga and N. R. Watson, Power Systems Electromagnetic Transients Simulation, IET Power and Energy Series 39 — source representation and control/network interfacing.
• A. B. Kahn, "Topological sorting of large networks," Communications of the ACM, vol. 5, no. 11, pp. 558-562, 1962 — the in-degree algorithm used to order the control blocks.

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