Excitation System (AC4A)

IEEE 421.5 Type AC4A excitation system / automatic voltage regulator: a high-initial-response alternator-rectifier exciter modeled as a fast voltage regulator that drives the machine field directly (no separate rotating-exciter integrator). Sense the generator terminal voltage Vt, form the error against the reference, clamp it with an input limiter [VIMIN, VIMAX], shape it with a (1+sTC)/(1+sTB) lead-lag, amplify with the regulator KA/(1+sTA), and output field voltage EFD bounded by [VRMIN, VRMAX - KC*Ifd]. When the rectifier loading factor KC is non-zero a field-current input Ifd appears and lowers the upper ceiling. Optional summing-point auxiliary inputs (PSS VS, under/over-excitation limiters VUEL/VOEL) and an optional external Vref override appear when enabled. Pairs with the synchronous machine for bumpless load-flow initialization. Also known as ESAC4A.

Category: Control / Excitation

Overview

The Type AC4A excitation system is the IEEE Std 421.5 model of a high-initial-response alternator-rectifier excitation system. Unlike the rotating-DC-exciter Type DC1A, the AC4A behaves like a fast static regulator: the voltage regulator output is the field voltage, with no separate exciter integrator in the forward path. Its defining feature is the field-current-dependent output ceiling VRMAX - KC*Ifd, which captures the commutating-reactance ("rectifier regulation") drop of the controlled-rectifier bridge as it loads up.

The component senses the machine terminal voltage Vt, compares it to the setpoint VREF, and outputs the field voltage EFD that wires into the synchronous machine's Efd input. With the optional load-flow auto-initialization (below) the whole regulator loop starts on its operating point, so a study begins in steady state with no excitation transient.

AC4A is also catalogued as ESAC4A in some libraries.

Block diagram

Signal flow, block by block (all quantities per-unit, $s=\mathrm{d}/\mathrm{d}t$):

1. Terminal-voltage transducer — the sensed voltage is a first-order filter of the machine terminal-voltage magnitude,

$$V_C=\frac{1}{1+s{T}_R}{V}_t.$$

AC4A commonly takes $T_R=0$ (direct sensing).

2. Summing junction — the voltage error drives the regulator,

$$V_{\text{err}}=V_{\text{ref}}-V_C+V_S+V_{UEL}+V_{OEL},$$

where $V_S,V_{UEL},V_{OEL}$ are the optional auxiliary inputs (all added — supply a signed signal; off by default). $V_{\text{ref}}$ is the regulator set-point — the auto-initialized vref0, unless the optional external Vref input is wired, which overrides it.

3. Input limiter — a windup clamp on the error,

$$V_I=\mathrm{clamp}(V_{\text{err}},V_{Imin},V_{Imax}).$$

4. Lead-lag (transient gain reduction) — a $(1+s{T}_C)/(1+s{T}_B)$ block trades static gain for transient phase lead. With $T_B=T_C=0$ it is a pass-through.

5. Regulator with a field-current-dependent ceiling — a high-gain lag whose non-windup output limit is reduced by the rectifier loading term,

$$E_{FD}=\mathrm{clamp}(\frac{K_A}{1+s{T}_A}{V}_I,V_{Rmin},V_{Rmax}-K_C{I}_{fd}).$$

The regulator output is the field voltage — there is no $1/(s{T}_E)$ exciter stage. The limit is non-windup: while $E_{FD}$ is pinned at a rail the regulator state is held there.

Rectifier loading (KC) and the field-current input

The AC family models the commutation voltage drop of the rectifier bridge with the constant $K_C$. The maximum field voltage the exciter can deliver falls as the field current rises:

$$E_{FD,max}=V_{Rmax}-K_C{I}_{fd}.$$

When $K_C\ne 0$ an Ifd input port appears; wire it from the machine's field-current output so the ceiling tracks the loading. With $K_C=0$ (the default) the model simplifies to a constant $V_{Rmax}$ ceiling and the Ifd port is hidden — a common and valid AC4A simplification.

Per-unit convention

Field voltage EFD is in the non-reciprocal per-unit system used throughout the excitation literature: $E_{FD}=1.0$ pu is the field voltage that produces rated terminal voltage on the air-gap line at no load. The machine's Efd input and Vt output use the same convention, so the exciter and machine plug together without scaling.

Auxiliary summing inputs

Three optional inputs sum into the regulator junction and are off by default (each adds its port only when enabled on the Aux Inputs tab):

Input	Enable	Sign at the junction	Typical source
VS	PSS input	added	power system stabilizer
VUEL	UEL input	added	under-excitation limiter
VOEL	OEL input	added	over-excitation limiter

This is the classic summing-point arrangement; the take-over (HV/LV gate) compositions of the standard are intentionally deferred. All three are added — supply each as a signed signal. When a port is enabled but left unconnected it reads zero, so it contributes nothing.

External voltage reference (Vref)

By default the regulator set-point $V_{\text{ref}}$ is the auto-initialized vref0. Enabling External Vref input on the Aux Inputs tab exposes a Vref input port that overrides that set-point. Because the port replaces the set-point, you must wire it when it is enabled: an enabled-but-unconnected Vref reads zero and collapses the reference. For a bumpless start, hold Vref at the auto-computed vref0 value (shown on the Initialization tab) through $t=0$, then apply any perturbation.

Load-flow auto-initialization

The exciter participates in the project's controller auto-initialization so a run starts bumpless. After the load-flow solves, the apply pass back-calculates the regulator setpoint and the state seeds so every derivative in the block diagram is zero at $t=0$:

• Pairing is wire-traced. The exciter declares that its EFD output drives a machine field; the initializer follows that wire (through GoTo/From labels) to the unique synchronous machine whose Efd it feeds. If the output fans out to more than one machine, or an intermediate block sits in the path, initialization is skipped with a warning rather than guessing.

• The field voltage matches the machine. $E_{FD}(0)$ is set to the same $e_{fd0}$ the paired machine derives from its load-flow operating point (shared back-calculation), and $V_C(0)$ to the machine terminal-voltage magnitude $V_t$.

• The setpoint balances the loop. Because the regulator output is the field voltage directly (no exciter stage, lead-lag DC gain $1$, input limiter inactive),

$$V_{\text{ref}}=V_t+\frac{E_{FD0}}{K_A}.$$

If the required field forcing exceeds the regulator limits a warning is emitted (the operating point is not reachable with the configured ceiling), but the best-effort seed is still proposed. The field-current term $K_C{I}_{fd}$ is applied at run time; the back-calc uses the constant $V_{Rmax}$ ceiling for its reachability warning.

These quantities populate VREF, EFD(0) and VC(0) on the Initialization tab. You normally never type them by hand; set them only when using the exciter standalone, in which case choose $V_{\text{ref}}=V_t+E_{FD0}/K_A$ to start flat.

Wiring

• Vt ← the synchronous machine's Vt output (terminal-voltage magnitude, pu).
• EFD → the synchronous machine's Efd input (field voltage, pu).
• Optionally Ifd ← the machine's field-current output (appears when KC != 0).
• Optionally VS / VUEL / VOEL ← a stabilizer or limiter model.
• Optionally Vref ← an external set-point source. When wired it overrides the internal vref0; hold it at the auto-computed value for a bumpless start.

Enable Monitor EFD / VC on the Monitoring tab to record the field voltage and sensed voltage as named signals for plotting.

When to use something else

• Rotating DC-commutator excitation: the Type DC1A model captures the $1/(s{T}_E)$ exciter field dynamics and its saturation; AC4A has no rotating exciter.
• A fixed field (no regulator): leave the machine's Efd unwired and use its constant $e_{fd0}$ fallback instead of an exciter.

Ports

Name	Direction	Value type	Notes
Vt	input	double
Ifd	input	double	Visible when KC != 0
Vref	input	double	Visible when enable_vref == 1
VS	input	double	Visible when enable_pss == 1
VUEL	input	double	Visible when enable_uel == 1
VOEL	input	double	Visible when enable_oel == 1
EFD	output	double

Parameters

Regulator

Name	Label	Type	Default	Units	Description
KA	KA	double	200	—	Voltage-regulator gain (pu EFD per pu voltage error). AC4A is a high-gain, high-initial-response regulator, so KA is large (typically 100-400).
TA	TA	double	0.015	s (s, ms)	Voltage-regulator time constant of the KA/(1+sTA) block. Small for the fast AC4A response.
VIMAX	VIMAX	double	10	—	Upper limit on the voltage error entering the lead-lag / regulator (pu). The AC4A input limiter clamps the summed error before the forward path; leave wide to keep it inactive.
VIMIN	VIMIN	double	-10	—	Lower limit on the voltage error entering the lead-lag / regulator (pu).
TC	TC	double	1	s (s, ms)	Lead-lag numerator (lead) time constant of the (1+sTC)/(1+sTB) transient-gain-reduction block. Leave TB = TC = 0 for a pass-through.
TB	TB	double	10	s (s, ms)	Lead-lag denominator (lag) time constant of the (1+sTC)/(1+sTB) block. With TB > TC it provides transient gain reduction for the high-gain loop.
VRMAX	VRMAX	double	5.64	—	Upper limit on the regulator output / field voltage EFD (pu). A non-windup limit. When KC != 0 the effective upper ceiling is VRMAX - KC*Ifd (rectifier regulation).
VRMIN	VRMIN	double	-4.53	—	Lower limit on the regulator output / field voltage EFD (pu). Negative values permit field forcing down (de-excitation).
TR	TR	double	0	s (s, ms)	Terminal-voltage transducer (sensing) time constant 1/(1+sTR). TR = 0 senses Vt directly (the common AC4A case). A small non-zero value makes the sensed voltage VC an integrator state seeded at the operating point.

Field Current Limit

Name	Label	Type	Default	Units	Description
KC	KC	double	0	—	Rectifier loading factor (commutating-reactance drop). When KC != 0 a field-current input Ifd appears and the upper output ceiling becomes VRMAX - KC*Ifd, modeling the AC4A's rectifier regulation. Leave KC = 0 (the default) for the simplified AC4A with a constant VRMAX ceiling and no Ifd input.

Aux Inputs

Name	Label	Type	Default	Units	Description
enable_vref	External Vref input (Vref)	enum (Off / On)	0	—	Expose an external voltage-reference input port Vref. When on, a Vref port appears and OVERRIDES (replaces) the regulator setpoint: the wired signal is used as VREF instead of the internal, auto-initialized vref0. Drive it from a constant or a step/ramp to study the regulator's reference response. You must wire it — an enabled but unconnected Vref reads 0 and collapses the reference. Leave off to use the auto-computed vref0.
enable_pss	PSS input (VS)	enum (Off / On)	0	—	Expose the summing-point auxiliary input VS for a power system stabilizer. When on, a VS input port appears and is added at the regulator summing junction.
enable_uel	UEL input (VUEL)	enum (Off / On)	0	—	Expose the summing-point auxiliary input VUEL for an under-excitation limiter. When on, a VUEL input port appears and is added at the regulator summing junction (supply a signed boosting signal).
enable_oel	OEL input (VOEL)	enum (Off / On)	0	—	Expose the summing-point auxiliary input VOEL for an over-excitation limiter. When on, a VOEL input port appears and is added at the regulator summing junction (supply a signed reducing signal).

Monitoring

Name	Label	Type	Default	Units	Description
measure_efd	Monitor EFD	enum (Off / On)	0	—	Record the field voltage EFD (pu) as a named observable.
measure_vc	Monitor VC	enum (Off / On)	0	—	Record the sensed (transduced) terminal voltage VC (pu) as a named observable.

Signal Names

Name	Label	Type	Default	Units	Description
efd_name	EFD name	string	(empty)	—	Observable name for the field voltage EFD. Blank = skip.
vc_name	VC name	string	(empty)	—	Observable name for the sensed terminal voltage VC. Blank = skip.

Initialization

Name	Label	Type	Default	Units	Description
vref0	VREF	double	1	—	Voltage-regulator setpoint reference (pu). Normally computed by the load-flow auto-initialization so the regulator starts in balance; set manually only for standalone use. Ignored at run time when the external Vref input is enabled and wired (the port overrides it).
efd_init	EFD(0)	double	1	—	Initial field voltage EFD at t = 0 (pu, non-reciprocal: 1.0 produces rated terminal voltage at no load). Seeds the regulator output state. Normally set by the load-flow auto-initialization from the paired machine's operating point.
vc_init	VC(0)	double	1	—	Initial sensed terminal voltage at t = 0 (pu). Seeds the transducer state. Normally set by the load-flow auto-initialization to the machine terminal-voltage magnitude.

Observables

Signal	Type	Default name	Enable	Description
EFD	signal	from efd_name	measure_efd	Field voltage EFD (pu, non-reciprocal) commanded to the machine's Efd input, after the [VRMIN, VRMAX - KC*Ifd] limit.
vc	signal	from vc_name	measure_vc	Sensed (transduced) terminal voltage VC (pu) after the 1/(1+sTR) transducer.