D-FF

Edge-triggered D flip-flop. On the active clock edge, the output q latches the value at d. Optional synchronous active-high reset.

Category: Digital Logic / Sequential

Ports

Name	Direction	Value type	Notes
d	input	int
clk	input	int
rst	input	int	Visible when has_rst == 1
q	output	int

Parameters

Name	Label	Type	Default	Units	Description
q0	q₀	int	0	—	Initial value of the stored state q at sim_time = 0.
has_rst	Reset port	enum (disabled / enabled)	0	—	When enabled, exposes a synchronous active-high reset port. On a clock rising edge, if rst != 0 then q := 0 (per-bit clear).