Excitation System (DC1A)

IEEE 421.5 Type DC1A excitation system / automatic voltage regulator: a DC-commutator exciter driven by a lead-lag + high-gain regulator, with terminal-voltage sensing, a rate (derivative) feedback loop, and exciter saturation. Sense the generator terminal voltage Vt, output field voltage EFD to the machine's Efd input. Optional summing-point auxiliary inputs (PSS VS, under/over-excitation limiters VUEL/VOEL) appear when enabled, plus an optional external Vref input that overrides the auto-initialized voltage-regulator setpoint for reference-step studies. Pairs with the synchronous machine for bumpless load-flow initialization.

Category: Control / Excitation

Overview

The Type DC1A excitation system is the IEEE Std 421.5 model of a DC-commutator exciter under automatic voltage regulation. A separately- (or self-) excited DC generator on the main shaft supplies the synchronous machine's field; a high-gain voltage regulator drives that exciter so the generator terminal voltage tracks a reference. It is the canonical model for older units whose excitation is provided by a rotating DC exciter rather than a static or AC-rectifier source, and it is the natural first member of the IEEE 421.5 family (the AC and ST types share the same regulator front-end).

The component senses the machine terminal voltage Vt, compares it to the setpoint VREF, and outputs the field voltage EFD that wires into the synchronous machine's Efd input. With the optional load-flow auto-initialization (below) the whole regulator → exciter loop starts on its operating point, so a study begins in steady state with no excitation transient.

Block diagram

Signal flow, block by block (all quantities per-unit, $s = d / d t$ ):

Terminal-voltage transducer — the sensed voltage is a first-order filter of the machine terminal-voltage magnitude,

V_{C} = \frac{1}{1 + s T_{R}} V_{t} .

Summing junction — the voltage error drives the regulator,

V_{err} = V_{ref} - V_{C} + V_{S} + V_{U E L} + V_{O E L} - V_{F},

where $V_{S}, V_{U E L}, V_{O E L}$ are the optional auxiliary inputs (all added — supply a signed signal; off by default, see below) and $V_{F}$ is the rate feedback. $V_{ref}$ is the regulator set-point — the auto-initialized vref0, unless the optional external Vref input is wired, which overrides it (see below).

Lead-lag (transient gain reduction) — an optional $(1 + s T_{C}) / (1 + s T_{B})$ block trades static gain for transient phase lead. With $T_{B} = T_{C} = 0$ it is a pass-through.
Regulator — a high-gain lag with a non-windup output limit,

V_{R} = clamp (\frac{K_{A}}{1 + s T_{A}} V_{L L}, V_{R min}, V_{R max}) .

The limit is non-windup: while $V_{R}$ is pinned at a rail the regulator state is held there, so it releases immediately when the error reverses.

DC exciter — an integrator with the exciter's own field characteristic in the feedback path,

T_{E} \frac{d E_{F D}}{d t} = V_{R} - \underset{V_{F E}}{\underset{⏟}{(K_{E} + S_{E} (E_{F D})) E_{F D}}} .

$K_{E}$ is the exciter self-excitation constant ( $K_{E} = 1$ for a separately-excited exciter); $S_{E} (E_{F D})$ is the saturation function.

Rate feedback — a stabilizing minor loop (a washout) from the exciter output back to the summing junction,

V_{F} = \frac{s K_{F}}{1 + s T_{F}} E_{F D},

which contributes nothing in steady state ( $V_{F} \to 0$ ) but adds the damping that makes the high-gain loop stable. Set $K_{F} = 0$ to remove it.

Exciter saturation

The exciter saturation $S_{E} (E_{F D})$ captures the departure of the DC exciter's field from the air-gap line as it approaches its ceiling. The model uses the quadratic (Schultz) form

S_{E} (E) = {\begin{cases} \frac{B (E - A)^{2}}{E} & E > A, \\ 0 & E \leq A, \end{cases}

fitted through the two datasheet points $(E_{1}, S_{E} (E_{1}))$ and $(E_{2}, S_{E} (E_{2}))$ that you enter on the Exciter tab (typically the ceiling voltage and $0.75 \times$ ceiling). Turning Exciter saturation off sets $S_{E} \equiv 0$ , i.e. a linear exciter with $V_{F E} = K_{E} E_{F D}$ .

Solving the two-point fit gives, with $r = \sqrt{S_{E} (E_{1}) E_{1} / (S_{E} (E_{2}) E_{2})}$ ,

A = \frac{r E_{2} - E_{1}}{r - 1}, B = \frac{S_{E} (E_{1}) E_{1}}{(E_{1} - A)^{2}} .

A degenerate or non-physical fit (either point zero, coincident points, $B < 0$ ) falls back to $S_{E} \equiv 0$ .

Per-unit convention

Field voltage EFD is in the non-reciprocal per-unit system used throughout the excitation literature: $E_{F D} = 1.0$ pu is the field voltage that produces rated terminal voltage on the air-gap line at no load. The machine's Efd input and Vt output use the same convention, so the exciter and machine pluggable without any scaling. Regulator and exciter limits ( $V_{R max}$ , $V_{R min}$ ) and the saturation breakpoints ( $E_{1}$ , $E_{2}$ ) are all in this same pu.

Auxiliary summing inputs

Three optional inputs sum into the regulator junction and are off by default (each adds its port only when enabled on the Aux Inputs tab):

Input	Enable	Sign at the junction	Typical source
VS	PSS input	added	power system stabilizer
VUEL	UEL input	added	under-excitation limiter
VOEL	OEL input	added	over-excitation limiter

This is the classic summing-point arrangement; the take-over (HV/LV gate) compositions of the standard are intentionally deferred. All three are added at the junction — supply each as a signed signal, so the connected model decides the direction (a stabilizer adds a damping component, an under-excitation limiter pushes the voltage up, an over-excitation limiter pushes it down). When a port is enabled but left unconnected it reads zero, so it contributes nothing.

External voltage reference (Vref)

By default the regulator set-point $V_{ref}$ is the auto-initialized vref0 (computed below). Enabling External Vref input on the Aux Inputs tab exposes a Vref input port that overrides that set-point: when wired, the regulator uses the Vref signal as $V_{ref}$ instead of vref0. Drive it from a constant, step, or ramp to study the voltage-regulator reference response (e.g. a set-point step test).

Because the port replaces the set-point, you must wire it when it is enabled: an enabled-but-unconnected Vref reads zero and collapses the reference (the field collapses to its lower rail). For a bumpless start, hold Vref at the auto-computed vref0 value (shown on the Initialization tab) through $t = 0$ , then apply any perturbation. Leave the toggle off to use the internally computed vref0.

Load-flow auto-initialization

The exciter participates in the project's controller auto-initialization so a run starts bumpless. After the load-flow solves, the apply pass back-calculates the regulator setpoint and the integrator seeds so every derivative in the block diagram is zero at $t = 0$ :

Pairing is wire-traced. The exciter declares that its EFD output drives a machine field; the initializer follows that wire (through GoTo/From labels) to the unique synchronous machine whose Efd it feeds. If the output fans out to more than one machine, or an intermediate block sits in the path, initialization is skipped with a warning rather than guessing.
The field voltage matches the machine. $E_{F D} (0)$ is set to the same $e_{f d 0}$ the paired machine derives from its load-flow operating point (shared back-calculation), and $V_{C} (0)$ to the machine terminal-voltage magnitude $V_{t}$ .
The setpoint balances the loop. From the steady state ( $d E_{F D} / d t = 0 \Rightarrow V_{R} = V_{F E} (E_{F D 0})$ ; $V_{F} = 0$ ; lead-lag DC gain $1$ ),

V_{F E 0} = (K_{E} + S_{E} (E_{F D 0})) E_{F D 0}, V_{R 0} = clamp (V_{F E 0}, V_{R min}, V_{R max}), V_{ref} = \frac{V_{R 0}}{K_{A}} + V_{t} .

If the required field forcing exceeds the regulator limits a warning is emitted (the operating point is not reachable with the configured ceiling), but the best-effort seed is still proposed.

These three quantities populate VREF, EFD(0) and VC(0) on the Initialization tab. You normally never type them by hand; set them only when using the exciter standalone (driven by a constant or external Vt), in which case choose $V_{ref} = V_{F E 0} / K_{A} + V_{t}$ to start flat.

Wiring

Vt ← the synchronous machine's Vt output (terminal-voltage magnitude, pu).
EFD → the synchronous machine's Efd input (field voltage, pu).
Optionally VS / VUEL / VOEL ← a stabilizer or limiter model.
Optionally Vref ← an external set-point source (constant / step / ramp). When wired it overrides the internal vref0; hold it at the auto-computed vref0 for a bumpless start.

Enable Monitor EFD / VC / VR on the Monitoring tab to record the field voltage, sensed voltage, and regulator output as named signals for plotting.

When to use something else

Static (bus-fed thyristor) or AC-rectifier excitation: the Type ST and AC models of IEEE 421.5 (forthcoming) capture the rectifier regulation and the absence of a rotating exciter; DC1A specifically models the DC-commutator exciter's $1 / (s T_{E})$ field dynamics and its saturation.
A fixed field (no regulator): leave the machine's Efd unwired and use its constant $e_{f d 0}$ fallback instead of an exciter.

Ports

Name	Direction	Value type	Notes
`Vt`	`input`	`double`
`Vref`	`input`	`double`	Visible when `enable_vref == 1`
`VS`	`input`	`double`	Visible when `enable_pss == 1`
`VUEL`	`input`	`double`	Visible when `enable_uel == 1`
`VOEL`	`input`	`double`	Visible when `enable_oel == 1`
`EFD`	`output`	`double`

Parameters

Regulator

Name	Label	Type	Default	Units	Description
`KA`	KA	`double`	`46`	—	Voltage-regulator gain (pu EFD per pu voltage error). Sets the static loop gain — higher KA gives tighter voltage regulation but reduces transient stability margin.
`TA`	TA	`double`	`0.06`	`s` (`s`, `ms`)	Voltage-regulator time constant. The dominant regulator lag KA/(1+sTA).
`TB`	TB	`double`	`0`	`s` (`s`, `ms`)	Lead-lag denominator (lag) time constant. Leave TB = TC = 0 for no transient gain reduction (the lead-lag becomes a pass-through).
`TC`	TC	`double`	`0`	`s` (`s`, `ms`)	Lead-lag numerator (lead) time constant of the (1+sTC)/(1+sTB) transient-gain-reduction block.
`VRMAX`	VRMAX	`double`	`5`	—	Upper limit on the regulator output VR (pu). A non-windup limit: the regulator state is held at the limit so it cannot wind up while pinned.
`VRMIN`	VRMIN	`double`	`-5`	—	Lower limit on the regulator output VR (pu). Negative values permit field forcing down (de-excitation).
`TR`	TR	`double`	`0.02`	`s` (`s`, `ms`)	Terminal-voltage transducer (sensing) time constant 1/(1+sTR). A small non-zero value (e.g. 0.02 s) is recommended so the sensed voltage VC is an integrator state seeded at the load-flow operating point, giving a bumpless start. TR = 0 senses Vt directly with no filtering.

Exciter

Name	Label	Type	Default	Units	Description
`KE`	KE	`double`	`1`	—	Exciter field self-excitation constant. The exciter loop is TEdEFD/dt = VR - (KE + SE(EFD))EFD. KE = 1 models a separately-excited exciter; small or negative values model a self-excited shunt field.
`TE`	TE	`double`	`0.46`	`s` (`s`, `ms`)	Exciter time constant (the integrator 1/(sTE) in the exciter loop).
`KF`	KF	`double`	`0.1`	—	Rate (derivative) feedback gain. The stabilizing minor loop sKF/(1+sTF) fed from EFD back to the summing junction. Set KF = 0 to disable the rate feedback.
`TF`	TF	`double`	`1`	`s` (`s`, `ms`)	Rate-feedback time constant of the sKF/(1+sTF) stabilizing loop.
`sat_enable`	Exciter saturation	enum (`Off` / `On`)	`1`	—	Model the exciter saturation function SE(EFD). When on, SE is fitted from the two datasheet points below; when off, SE(EFD) = 0 (linear exciter).
`E1`	E1	`double`	`3.1`	—	Higher exciter-voltage saturation point (pu EFD), typically the exciter ceiling voltage.
`SE1`	SE(E1)	`double`	`0.33`	—	Saturation factor at E1 (dimensionless). The fitted curve SE(E) = B*(E-A)^2/E passes through (E1, SE1).
`E2`	E2	`double`	`2.3`	—	Lower exciter-voltage saturation point (pu EFD), typically 0.75 * E1.
`SE2`	SE(E2)	`double`	`0.1`	—	Saturation factor at E2 (dimensionless). The fitted curve SE(E) = B*(E-A)^2/E passes through (E2, SE2).

Aux Inputs

Name	Label	Type	Default	Units	Description
`enable_vref`	External Vref input (Vref)	enum (`Off` / `On`)	`0`	—	Expose an external voltage-reference input port Vref. When on, a Vref port appears and OVERRIDES (replaces) the regulator setpoint: the wired signal is used as VREF instead of the internal, auto-initialized vref0. Drive it from a constant or a step/ramp to study the regulator's reference response. You must wire it — an enabled but unconnected Vref reads 0 and collapses the reference. Leave off to use the auto-computed vref0.
`enable_pss`	PSS input (VS)	enum (`Off` / `On`)	`0`	—	Expose the summing-point auxiliary input VS for a power system stabilizer. When on, a VS input port appears and is added at the regulator summing junction.
`enable_uel`	UEL input (VUEL)	enum (`Off` / `On`)	`0`	—	Expose the summing-point auxiliary input VUEL for an under-excitation limiter. When on, a VUEL input port appears and is added at the regulator summing junction (supply a signed boosting signal).
`enable_oel`	OEL input (VOEL)	enum (`Off` / `On`)	`0`	—	Expose the summing-point auxiliary input VOEL for an over-excitation limiter. When on, a VOEL input port appears and is added at the regulator summing junction (supply a signed reducing signal).

Monitoring

Name	Label	Type	Default	Units	Description
`measure_efd`	Monitor EFD	enum (`Off` / `On`)	`0`	—	Record the field voltage EFD (pu) as a named observable.
`measure_vc`	Monitor VC	enum (`Off` / `On`)	`0`	—	Record the sensed (transduced) terminal voltage VC (pu) as a named observable.
`measure_vr`	Monitor VR	enum (`Off` / `On`)	`0`	—	Record the regulator output VR (pu, after the [VRMIN, VRMAX] limit) as a named observable.

Signal Names

Name	Label	Type	Default	Units	Description
`efd_name`	EFD name	`string`	(empty)	—	Observable name for the field voltage EFD. Blank = skip.
`vc_name`	VC name	`string`	(empty)	—	Observable name for the sensed terminal voltage VC. Blank = skip.
`vr_name`	VR name	`string`	(empty)	—	Observable name for the regulator output VR. Blank = skip.

Initialization

Name	Label	Type	Default	Units	Description
`vref0`	VREF	`double`	`1`	—	Voltage-regulator setpoint reference (pu). Normally computed by the load-flow auto-initialization so the regulator starts in balance; set manually only for standalone use. Ignored at run time when the external Vref input is enabled and wired (the port overrides it) — in that case drive Vref to this value for a bumpless start.
`efd_init`	EFD(0)	`double`	`1`	—	Initial field voltage EFD at t = 0 (pu, non-reciprocal: 1.0 produces rated terminal voltage at no load). Seeds the exciter integrator. Normally set by the load-flow auto-initialization from the paired machine's operating point.
`vc_init`	VC(0)	`double`	`1`	—	Initial sensed terminal voltage at t = 0 (pu). Seeds the transducer state. Normally set by the load-flow auto-initialization to the machine terminal-voltage magnitude.

Observables

Signal	Type	Default name	Enable	Description
`EFD`	`signal`	from `efd_name`	`measure_efd`	Field voltage EFD (pu, non-reciprocal) commanded to the machine's Efd input.
`vc`	`signal`	from `vc_name`	`measure_vc`	Sensed (transduced) terminal voltage VC (pu) after the 1/(1+sTR) transducer.
`vr`	`signal`	from `vr_name`	`measure_vr`	Regulator output VR (pu) after the KA/(1+sTA) block and the [VRMIN, VRMAX] limit.

Excitation System (DC1A) ​

Overview ​

Block diagram ​

Exciter saturation ​

Per-unit convention ​

Auxiliary summing inputs ​

External voltage reference (Vref) ​

Load-flow auto-initialization ​

Wiring ​

When to use something else ​

Ports ​

Parameters ​

Regulator ​

Exciter ​

Aux Inputs ​

Monitoring ​

Signal Names ​

Initialization ​

Observables ​