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Flip-Flop
Edge-triggered D, JK, RS or T flip-flop, chosen with the Type parameter. On each rising clock edge: D latches d; JK sets on J, resets on K and toggles when J = K = 1; RS sets on S, resets on R and holds on the invalid S = R = 1 instead of toggling; T toggles when t = 1 and holds when t = 0. Inputs and the stored state are integers evaluated bitwise. Optional synchronous active-high reset.
Category: Digital Logic / Sequential
Overview
The Flip-Flop block is every edge-triggered flip-flop in one part. Pick the kind with Type — D, JK, RS or T — and the input pins and their letters on the body redraw to match. Changing Type removes the wires on input pins the new type does not have.
All four types clock the same way, matching the Counter: a rising edge is clk going from 0 to non-zero. Between edges, q does not change. The starting value is q₀.
Inputs and the stored state are integers evaluated bitwise, so one block can store a whole word of flags. Drive it with 0/1 signals for ordinary single-bit logic.
Truth tables
Evaluated per bit, on a rising clock edge.
D
| D | Q next |
|---|---|
| 0 | 0 |
| 1 | 1 |
The output is the input sampled at the last clock edge.
T
| T | Q next |
|---|---|
| 0 | hold (Q) |
| 1 | not Q (toggle) |
With T held at 1 the output is the clock divided by two.
JK
| J | K | Q next |
|---|---|---|
| 0 | 0 | hold (Q) |
| 1 | 0 | 1 (set) |
| 0 | 1 | 0 (reset) |
| 1 | 1 | not Q (toggle) |
With J and K tied together, the JK type behaves like the T type.
RS
| S | R | Q next |
|---|---|---|
| 0 | 0 | hold (Q) |
| 1 | 0 | 1 (set) |
| 0 | 1 | 0 (reset) |
| 1 | 1 | hold (Q) |
S = R = 1 is the classic forbidden input of an RS latch. This model holds the previous state so the behaviour is defined and deterministic. It does not toggle; pick the JK type when both inputs high should toggle.
Reset port
The optional rst pin (enable Reset port in Config) is a synchronous active-high clear of every bit. When rst is non-zero on a rising edge, q becomes 0 regardless of the data inputs.
On the RS type this is different from the R pin: R only clears the bits where R is 1, while rst clears all of them.
Related
- Counter — same clocking rule
- Clock — square-wave clock source
- Logic Gate — combinational logic for the flip-flop inputs
- Flip-flop truth tables — all four types driven by the same stimulus on one plot
Ports
| Port | Kind | Signal | Notes |
|---|---|---|---|
d | Control input | Integer | Shown when Type is D |
j | Control input | Integer | Shown when Type is JK |
k | Control input | Integer | Shown when Type is JK |
s | Control input | Integer | Shown when Type is RS |
r | Control input | Integer | Shown when Type is RS |
t | Control input | Integer | Shown when Type is T |
clk | Control input | Integer | |
rst | Control input | Integer | Shown when Reset port is enabled |
q | Control output | Integer |
Parameters
| Parameter | Type | Default | Units | Description | ID |
|---|---|---|---|---|---|
| Type | Choice: D / JK / RS / T | D | — | D: q := d. JK: J sets, K resets, J = K = 1 toggles, J = K = 0 holds. RS: S sets, R resets, S = R = 0 and S = R = 1 both hold. T: t = 1 toggles, t = 0 holds. Every type acts only on a rising clock edge. | ff_type |
| q₀ | Integer | 0 | — | Initial value of the stored state q at sim_time = 0. | q0 |
| Reset port | Choice: disabled / enabled | disabled | — | When enabled, exposes a synchronous active-high reset port. On a clock rising edge, if rst != 0 then q := 0 (per-bit clear). | has_rst |