Excitation System (AC1A)

IEEE 421.5 Type AC1A excitation system / automatic voltage regulator: a field-controlled alternator exciter feeding the generator field through non-controlled (diode) rectifiers, implemented to the AC1C block diagram, which accepts AC1A data unchanged. Sense the terminal voltage Vt, form the voltage error against the reference, shape it with a lead-lag (1+sTC)/(1+sTB), amplify with the regulator KA/(1+sTA) bounded by [VAMIN, VAMAX], pass the UEL / OEL take-over gates and the exciter field-voltage limit [VRMIN, VRMAX], and drive the rotating exciter 1/(sTE) whose field current VFE = VE*(KE + SE(VE)) + KDIfd carries saturation and armature demagnetization. The output EFD = VEFEX(KCIfd/VE) carries the rectifier regulation drop. Rate feedback KFs/(1+sTF) from VFE, optional PSS / UEL / OEL inputs (UEL / OEL summed or through take-over gates), AC1C's VEMIN / VFEMAX exciter limits, and an optional external Vref override. Pairs with the synchronous machine for bumpless load-flow initialization. Also known as AC1C, ESAC1A and EXAC1.

Category: Control / Excitation

Overview

The Type AC1A excitation system is the IEEE Std 421.5 model of a field-controlled alternator-rectifier exciter: a rotating alternator on the generator shaft feeds the field through non-controlled (diode) rectifiers, and the voltage regulator controls the alternator's own field. The regulator's supply does not depend on the generator terminals, so a close-in fault does not collapse the forcing, but the rotating exciter's field time constant makes the response far slower than a static bridge. Brushless exciters are the typical application.

This component implements the block diagram of the newer Type AC1C model (IEEE Std 421.5-2016, Figures 8 and 9). AC1C accepts AC1A data unchanged once its two extra exciter limits sit at their AC1A values (VEMIN = 0, VFEMAX = 99, the defaults). The model senses the machine terminal voltage Vt and the field current Ifd, and outputs the field voltage EFD that wires into the synchronous machine's Efd input. With the load-flow auto-initialization (below) the exciter starts on its operating point, so a study begins in steady state with no excitation transient.

AC1A is also catalogued as AC1C, ESAC1A and EXAC1 in some libraries.

Block diagram

Signal flow, block by block (all quantities per-unit, $s=\mathrm{d}/\mathrm{d}t$):

1. Terminal-voltage transducer —

$$V_C=\frac{1}{1+s{T}_R}{V}_t.$$

2. Voltage error —

$$V_{err}=V_{\text{ref}}-V_C-V_F+V_S+V_{UEL}^{(a)}+V_{OEL}^{(a)},$$

where the superscript marks a limiter connected at location (a) (see Alternate input locations). $V_{\text{ref}}$ is the auto-initialized vref0, unless the optional external Vref input is wired, which overrides it.

3. Lead-lag — $(1+s{T}_C)/(1+s{T}_B)$; both time constants zero is a pass-through.

4. Regulator — $V_A={\displaystyle \frac{K_A}{1+s{T}_A}}{V}_{LL}$, held inside $[V_{Amin},V_{Amax}]$ by a non-windup limit.

5. Take-over gates and exciter field-voltage limit — an HV gate $max(V_A,V_{UEL})$ and an LV gate $min(\cdot ,V_{OEL})$ (location b), then $V_R=\mathrm{clamp}(\cdot ,V_{Rmin},V_{Rmax})$. AC1C calls these limits $E_{FEmin}$ / $E_{FEmax}$.

6. Rotating exciter —

$$T_E\frac{\mathrm{d}{V}_E}{\mathrm{d}t}=V_R-V_{FE},V_{FE}=V_E(K_E+S_E(V_E))+K_D{I}_{fd}.$$

7. Rectifier regulation —

$$E_{FD}=V_E{F}_{EX}(I_N),I_N=\frac{K_C{I}_{fd}}{V_E}.$$

8. Rate feedback — $V_F={\displaystyle \frac{s{K}_F}{1+s{T}_F}}{V}_{FE}$, taken from the exciter field current and zero in steady state. It is off when $K_F=0$ or $T_F=0$.

The rotating exciter

The exciter field current $V_{FE}$ balances the exciter field voltage $V_R$ in steady state. Three terms make it up:

• $K_E{V}_E$, the unsaturated field requirement.
• $V_E{S}_E(V_E)$, saturation. $S_E$ is the two-point quadratic fit through $(E_1,S_E(E_1))$ and $(E_2,S_E(E_2))$, evaluated on the exciter output $V_E$. Set both factors to 0 for an unsaturated exciter.
• $K_D{I}_{fd}$, armature reaction: the generator's field current loads the alternator and demagnetizes it, so holding the same $V_E$ takes more exciter field. A rise in $I_{fd}$ therefore lowers $V_E$ over $T_E$ until the regulator catches up.

The integrator is held inside two non-windup limits:

• $V_E\ge V_{Emin}$: the diodes cannot reverse the exciter output, so AC1A uses 0.
• $V_E\le (V_{FEmax}-K_D{I}_{fd})/(K_E+S_E(V_E))$, which keeps $V_{FE}\le V_{FEmax}$. This is AC1C's instantaneous exciter field-current limit. Leave $V_{FEmax}=99$ (never binds) when an explicit over-excitation limiter model protects the field, so the two do not act together.

With $T_E=0$ the exciter becomes algebraic: $V_E$ settles within the time step to the value whose $V_{FE}$ equals $V_R$ (capped at $V_{FEmax}$). Real AC1A data always has $T_E>0$.

Rectifier regulation

The diode bridge's commutating reactance drops the output as the field current rises. IEEE Std 421.5 Annex D expresses the drop through the normalized load $I_N=K_C{I}_{fd}/V_E$:

Mode	Range	$F_{EX}$
1	$I_N\le 0.433$	$1-0.577I_N$
2	$0.433<I_N<0.75$	$\sqrt{0.75-I_N^2}$
3	$0.75\le I_N\le 1$	$1.732(1-I_N)$
—	$I_N>1$	$0$

The drop acts instantly: $E_{FD}$ follows every change in $I_{fd}$ through $F_{EX}$, with no time constant. When $K_C$ or $K_D$ is non-zero an Ifd input port appears; wire it from the machine's field-current output. With both zero the port is hidden and the field current plays no part.

Alternate input locations

The PSS input VS always adds at the voltage error. Each limiter input can connect at one of two points; pick it on the Aux Inputs tab after enabling the input:

Input	(a)	(b)
VUEL (under-excitation limiter)	added to the voltage error	HV gate on the regulator output
VOEL (over-excitation limiter)	added to the voltage error	LV gate on the regulator output

Location (b) is the AC1A placement and the default; (a) is the AC1C addition, and the placement of the older EXAC1 model. A summation input that is enabled but unwired reads zero; a take-over gate whose input is unwired is a pass-through.

Per-unit convention

Field voltage EFD is in the non-reciprocal per-unit system: $E_{FD}=1.0$ pu produces rated terminal voltage on the air-gap line at no load. The machine's Efd input, Ifd output and Vt output use the same convention, so the exciter and machine plug together without scaling.

External voltage reference (Vref)

Enabling External Vref input exposes a Vref port that overrides the auto-initialized set-point. Because the port replaces the set-point, you must wire it when it is enabled: an unconnected Vref reads zero and collapses the reference. For a bumpless start, hold Vref at the auto-computed vref0 (shown on the Initialization tab) through $t=0$.

Load-flow auto-initialization

After the load flow solves, the apply pass back-calculates the set-point and the state seeds so every derivative in the diagram is zero at $t=0$:

• Pairing is wire-traced. The initializer follows the EFD wire (through GoTo/From labels) to the unique synchronous machine whose Efd it feeds. Fan-out to several machines, or an intermediate block in the path, skips initialization with a warning.
• The exciter voltage comes from the rectifier inverse. At rest the machine reports $I_{fd}=E_{FD0}$, its field voltage. Each $F_{EX}$ mode inverts in closed form,

$$V_E=E_{FD}+0.577K_C{I}_{fd},V_E=\sqrt{\frac{E_{FD}^2+(K_C{I}_{fd}{)}^2}{0.75}},V_E=\frac{E_{FD}}{1.732}+K_C{I}_{fd},$$

and the initializer keeps the one whose own $I_N$ lands in its mode.

• The set-point balances the loop. With the lead-lag at DC gain 1, the rate feedback washed out and the gates idle,

$$V_R=V_A=V_{FE0}=V_{E0}(K_E+S_E(V_{E0}))+K_D{I}_{fd0},V_{\text{ref}}=V_t+\frac{V_A}{K_A}.$$

Initialization is skipped when no $V_E\ge 0$ delivers the machine's field voltage (a negative field voltage, or a negative $K_C$). A warning is raised, and the best-effort seed still proposed, when $V_A$ or $V_R$ falls outside its limits, when $V_{E0}$ is below $V_{Emin}$, or when $V_{FE0}$ exceeds $V_{FEmax}$.

These quantities populate VREF, VC(0), VE(0) and IFD(0) on the Initialization tab. On the first time step the model also uses $V_C(0)$ and $I_{fd}(0)$ in place of the not-yet-available Vt and Ifd signals, so the regulator does not kick at $t=0$.

Wiring

• Vt ← the synchronous machine's Vt output.
• EFD → the synchronous machine's Efd input.
• Ifd ← the machine's field-current output (appears when KC != 0 or KD != 0).
• Optionally VS / VUEL / VOEL ← a stabilizer or limiter model, at the location chosen on the Aux Inputs tab.
• Optionally Vref ← an external set-point source.

Enable Monitor EFD / VC / VA / VE / VFE on the Monitoring tab to record the field voltage, the sensed voltage, the regulator output, the exciter output and the exciter field current.

When to use something else

• A static (bus-fed thyristor) exciter: use Type ST1A, whose ceiling follows the terminal voltage and which responds almost instantly.
• A high-initial-response alternator exciter modeled as a fast regulator: use Type AC4A.
• A rotating DC commutator exciter: use Type DC1A.

Ports

Name	Direction	Value type	Notes
Vt	input	double
Ifd	input	double	Visible when `KC != 0
Vref	input	double	Visible when enable_vref == 1
VS	input	double	Visible when enable_pss == 1
VUEL	input	double	Visible when enable_uel == 1
VOEL	input	double	Visible when enable_oel == 1
EFD	output	double

Parameters

Regulator

Name	Label	Type	Default	Units	Description
TR	TR	double	0	s (s, ms)	Terminal-voltage transducer (sensing) time constant 1/(1+sTR). TR = 0 senses Vt directly.
TC	TC	double	0	s (s, ms)	Lead-lag numerator (lead) time constant of (1+sTC)/(1+sTB). Leave TB = TC = 0 to bypass.
TB	TB	double	0	s (s, ms)	Lead-lag denominator (lag) time constant of (1+sTC)/(1+sTB). With TB = 0 the block is a pure lead 1+sTC (or a pass-through when TC = 0 too).
KA	KA	double	400	—	Voltage-regulator gain (pu exciter field voltage per pu voltage error).
TA	TA	double	0.02	s (s, ms)	Voltage-regulator time constant of the KA/(1+sTA) block. TA = 0 makes the regulator a pure gain.
VAMAX	VAMAX	double	14.5	—	Upper non-windup limit on the regulator output VA (pu).
VAMIN	VAMIN	double	-14.5	—	Lower non-windup limit on the regulator output VA (pu).
KF	KF	double	0.03	—	Rate-feedback gain of the sKF/(1+sTF) stabilizing loop, taken from the exciter field current VFE.
TF	TF	double	1	s (s, ms)	Rate-feedback time constant. The feedback is disabled when KF = 0 or TF = 0.

Exciter

Name	Label	Type	Default	Units	Description
VRMAX	VRMAX	double	6.03	—	Maximum exciter field voltage (pu): the upper limit on VR after the take-over gates. Called EFEmax in AC1C.
VRMIN	VRMIN	double	-5.43	—	Minimum exciter field voltage (pu). Called EFEmin in AC1C.
TE	TE	double	0.8	s (s, ms)	Exciter field time constant of the 1/(sTE) integrator. TE = 0 makes the exciter algebraic: VE settles within the step so that VFE = VR.
KE	KE	double	1	—	Exciter field proportional constant: the unsaturated slope of the exciter field current VFE against the exciter output VE.
E1	E1	double	4.18	—	Exciter output voltage VE at the first saturation point (pu).
SE1	SE(E1)	double	0.1	—	Exciter saturation factor SE(E1) at E1. Set SE1 = SE2 = 0 for an unsaturated exciter.
E2	E2	double	3.14	—	Exciter output voltage VE at the second saturation point (pu).
SE2	SE(E2)	double	0.03	—	Exciter saturation factor SE(E2) at E2.
KC	KC	double	0.2	—	Rectifier loading factor, proportional to the commutating reactance. EFD = VE * FEX(KC*Ifd/VE). When KC or KD is non-zero a field-current input Ifd appears.
KD	KD	double	0.38	—	Demagnetizing factor, a function of the exciter alternator reactances: KD*Ifd adds to the exciter field current VFE.
VEMIN	VEMIN	double	0	—	Lower limit on the exciter output VE (pu). 0 for the diode rectifier of AC1A; an AC1C parameter.
VFEMAX	VFEMAX	double	99	—	Upper limit on the exciter field current VFE (pu), applied as the VE ceiling (VFEMAX - KD*Ifd)/(KE + SE(VE)). 99 (never binds) reproduces AC1A; an AC1C parameter. Leave it at 99 when an OEL model protects the field.

Aux Inputs

Name	Label	Type	Default	Units	Description
enable_vref	External Vref input (Vref)	enum (Off / On)	0	—	Expose an external voltage-reference input port Vref. When on, a Vref port appears and OVERRIDES (replaces) the regulator setpoint: the wired signal is used as VREF instead of the internal, auto-initialized vref0. You must wire it - an enabled but unconnected Vref reads 0 and collapses the reference. Leave off to use the auto-computed vref0.
enable_pss	PSS input (VS)	enum (Off / On)	0	—	Expose the stabilizer input VS for a power system stabilizer. VS is added at the voltage-error summing junction.
enable_uel	UEL input (VUEL)	enum (Off / On)	0	—	Expose the under-excitation limiter input VUEL. Where it enters is set by UEL location.
uel_location	UEL location	enum (Summation at voltage error (a) / Take-over at regulator output (b))	2	—	Where VUEL enters: added at the voltage-error junction (a), or through an HV (take-over) gate on the regulator output (b), the AC1A placement.
enable_oel	OEL input (VOEL)	enum (Off / On)	0	—	Expose the over-excitation limiter input VOEL. Where it enters is set by OEL location.
oel_location	OEL location	enum (Summation at voltage error (a) / Take-over at regulator output (b))	2	—	Where VOEL enters: added at the voltage-error junction (a), or through an LV (take-over) gate after the HV gate (b), the AC1A placement.

Monitoring

Name	Label	Type	Default	Units	Description
measure_efd	Monitor EFD	enum (Off / On)	0	—	Record the field voltage EFD (pu) as a named observable.
measure_vc	Monitor VC	enum (Off / On)	0	—	Record the sensed (transduced) terminal voltage VC (pu) as a named observable.
measure_va	Monitor VA	enum (Off / On)	0	—	Record the regulator output VA (pu, after its [VAMIN, VAMAX] limit) as a named observable.
measure_ve	Monitor VE	enum (Off / On)	0	—	Record the exciter output voltage VE (pu) as a named observable.
measure_vfe	Monitor VFE	enum (Off / On)	0	—	Record the exciter field current VFE (pu) as a named observable.

Signal Names

Name	Label	Type	Default	Units	Description
efd_name	EFD name	string	(empty)	—	Observable name for the field voltage EFD. Blank = skip.
vc_name	VC name	string	(empty)	—	Observable name for the sensed terminal voltage VC. Blank = skip.
va_name	VA name	string	(empty)	—	Observable name for the regulator output VA. Blank = skip.
ve_name	VE name	string	(empty)	—	Observable name for the exciter output voltage VE. Blank = skip.
vfe_name	VFE name	string	(empty)	—	Observable name for the exciter field current VFE. Blank = skip.

Initialization

Name	Label	Type	Default	Units	Description
vref0	VREF	double	1	—	Voltage-regulator setpoint reference (pu). Normally computed by the load-flow auto-initialization so the regulator starts in balance; set manually only for standalone use. Ignored at run time when the external Vref input is enabled and wired (the port overrides it).
vc_init	VC(0)	double	1	—	Initial sensed terminal voltage at t = 0 (pu). Seeds the transducer state and stands in for Vt on the first step. Normally set by the load-flow auto-initialization to the machine terminal-voltage magnitude.
ve_init	VE(0)	double	1	—	Initial exciter output voltage VE at t = 0 (pu): the value whose rectified output VE * FEX(KC*Ifd/VE) is the machine's field voltage. Seeds the exciter integrator; the regulator and rate-feedback states follow from it. Normally set by the load-flow auto-initialization.
ifd_init	IFD(0)	double	1	—	Initial machine field current at t = 0 (pu, equal to the field voltage at rest). Seeds the exciter field current and stands in for Ifd on the first step. Normally set by the load-flow auto-initialization.

Observables

Signal	Type	Default name	Enable	Description
EFD	signal	from efd_name	measure_efd	Field voltage EFD = VEFEX(KCIfd/VE) (pu, non-reciprocal) commanded to the machine's Efd input.
vc	signal	from vc_name	measure_vc	Sensed (transduced) terminal voltage VC (pu) after the 1/(1+sTR) transducer.
va	signal	from va_name	measure_va	Regulator output VA (pu) after its [VAMIN, VAMAX] limit, before the take-over gates.
ve	signal	from ve_name	measure_ve	Exciter output voltage VE (pu): the exciter integrator state, before the rectifier regulation.
vfe	signal	from vfe_name	measure_vfe	Exciter field current VFE = VE*(KE + SE(VE)) + KD*Ifd (pu).

Used in samples

• Governor Island Load Step