RS-FF

Edge-triggered RS (set-reset) flip-flop. S=1 sets, R=1 resets, S=R=0 holds. S=R=1 is invalid and holds the previous state (does not toggle). Optional synchronous active-high reset.

Category: Digital Logic / Sequential

Overview

The RS-FF is an edge-triggered set-reset flip-flop. On each rising clock edge it sets q when S is 1, resets q when R is 1, and holds when both are 0. Inputs and the stored state are integers evaluated bitwise, same as the rest of the sequential digital family.

Clocking matches the other flip-flops and the Counter: a rising edge is clk going from 0 to non-zero. Between edges, q does not change.

Truth table

Evaluated per bit, on a rising clock edge:

S	R	Q next
0	0	hold (Q)
1	0	1 (set)
0	1	0 (reset)
1	1	hold (Q)

S = R = 1 is the classic forbidden input of an RS latch. This model holds the previous state so the behaviour is defined and deterministic. It does not toggle — that is the JK-FF.

Reset port vs R

The R pin is the clocked reset input of the RS pair: it only acts on a rising edge, and only on the bits where R is 1.

The optional rst pin (enable Reset port in Config) is a synchronous active-high clear of every bit. When rst is non-zero on a rising edge, q becomes 0 regardless of S and R.

Related

• D-FF — latches D
• JK-FF — set / reset / toggle
• T-FF — toggle when T is 1

Ports

Name	Direction	Value type	Notes
s	input	int
clk	input	int
r	input	int
rst	input	int	Visible when has_rst == 1
q	output	int

Parameters

Name	Label	Type	Default	Units	Description
q0	q₀	int	0	—	Initial value of the stored state q at sim_time = 0.
has_rst	Reset port	enum (disabled / enabled)	0	—	When enabled, exposes a synchronous active-high reset port. On a clock rising edge, if rst != 0 then q := 0 (per-bit clear).

Used in samples

• Flip Flop Truth Tables