Excitation System (ST1A)

IEEE 421.5 Type ST1A excitation system / automatic voltage regulator: a potential-source controlled-rectifier (static) exciter fed from the generator terminals, implemented to the ST1C block diagram, which accepts ST1A data unchanged. Sense the terminal voltage Vt, form the voltage error against the reference, clamp it [VIMIN, VIMAX], shape it with two lead-lags (1+sTC)/(1+sTB) and (1+sTC1)/(1+sTB1), amplify with the regulator KA/(1+sTA) bounded by [VAMIN, VAMAX], subtract the field-current limiter KLRmax(0, Ifd - ILR), and output field voltage EFD bounded by the terminal-voltage-proportional ceiling [VtVRMIN, VtVRMAX - KCIfd]. Optional rate feedback KF*s/(1+sTF) from EFD, optional PSS / UEL / OEL inputs at the standard's alternate locations (summation or take-over gate), and an optional external Vref override. Pairs with the synchronous machine for bumpless load-flow initialization. Also known as ST1C and ESST1A.

Category: Control / Excitation

Overview

The Type ST1A excitation system is the IEEE Std 421.5 model of a potential-source controlled-rectifier (static) exciter: a transformer fed from the generator terminals supplies a thyristor bridge that drives the field directly. There is no rotating exciter, so the response is almost instantaneous, and the field-voltage ceiling follows the terminal voltage — a close-in fault that collapses $V_{t}$ also collapses the forcing the bridge can deliver.

This component implements the block diagram of the newer Type ST1C model (IEEE Std 421.5-2016, Figure 21). ST1C accepts ST1A data unchanged; it only adds more choices for where an over-excitation limiter connects. The model senses the machine terminal voltage Vt and outputs the field voltage EFD that wires into the synchronous machine's Efd input. With the load-flow auto-initialization (below) the regulator starts on its operating point, so a study begins in steady state with no excitation transient.

ST1A is also catalogued as ST1C and ESST1A in some libraries.

Block diagram

Signal flow, block by block (all quantities per-unit, $s = d / d t$ ):

Terminal-voltage transducer —

V_{C} = \frac{1}{1 + s T_{R}} V_{t} .

Voltage error and input limiter —

V_{I} = clamp (V_{ref} - V_{C} - V_{F} + V_{S}^{(a)} + V_{U E L}^{(a)} + V_{O E L}^{(a)}, V_{I min}, V_{I max}),

where the superscript marks an input connected at location (a) (see Alternate input locations). $V_{ref}$ is the auto-initialized vref0, unless the optional external Vref input is wired, which overrides it.

Take-over gates at the voltage error (location b) — an HV gate $V_{I} = max (V_{I}, V_{U E L})$ and an LV gate $V_{I} = min (V_{I}, V_{O E L})$ , each present only when its limiter is connected there.
Two lead-lags — $(1 + s T_{C}) / (1 + s T_{B})$ provides transient gain reduction when $T_{B} > T_{C}$ ; $(1 + s T_{C 1}) / (1 + s T_{B 1})$ provides transient gain increase when $T_{C 1} > T_{B 1}$ . A block with both time constants zero is a pass-through.
Regulator — $V_{A} = \frac{K_{A}}{1 + s T_{A}} V_{L L}$ , held inside $[V_{A min}, V_{A max}]$ by a non-windup limit. $T_{A} = 0$ is common for a thyristor bridge.
Field-current limiter and regulator-output inputs —

V = V_{A} - K_{L R} max (0, I_{f d} - I_{L R}) + V_{S}^{(b)},

followed by the location-(c) gates $max (\cdot, V_{U E L})$ and $min (\cdot, V_{O E L})$ .

Terminal-voltage-proportional ceiling —

E_{F D} = clamp (V, V_{t} V_{R min}, V_{t} V_{R max} - K_{C} I_{f d}) .

Rate feedback — $V_{F} = \frac{s K_{F}}{1 + s T_{F}} E_{F D}$ , zero in steady state. It is off when $K_{F} = 0$ (the usual case when the lead-lag does the transient gain reduction) or $T_{F} = 0$ .

Field-voltage limits and the field-current input

Two terms load the bridge as the field current rises:

Commutation drop $K_{C} I_{f d}$ lowers the ceiling. Static bridges operate in the first rectifier mode, where this linear term is exact.
Field-current limiter $K_{L R} (I_{f d} - I_{L R})$ pulls the regulator output back once the field current passes the threshold $I_{L R}$ . Set $K_{L R} = 0$ when an explicit over-excitation limiter model protects the field instead — the two should not act together.

When $K_{C}$ or $K_{L R}$ is non-zero an Ifd input port appears; wire it from the machine's field-current output. With both zero the port is hidden and the field current plays no part.

Because the ceiling scales with $V_{t}$ , set $V_{R min} = 0$ for a half-controlled bridge that cannot force negative field voltage.

Alternate input locations

The standard lets each auxiliary input connect at one of several points. Pick the point on the Aux Inputs tab after enabling the input:

Input	(a)	(b)	(c)
VS (PSS)	added to the voltage error	added at the regulator output	—
VUEL (under-excitation limiter)	added to the voltage error	HV gate on the voltage error	HV gate on the regulator output
VOEL (over-excitation limiter)	added to the voltage error	LV gate on the voltage error	LV gate on the regulator output

Location (c) for VOEL is the only one the original ST1A model had, so it is the default; (a) and (b) are the ST1C additions. The location codes match the UEL and VOS codes of an ESST1A record. A summation input that is enabled but unwired reads zero; a take-over gate whose input is unwired is a pass-through.

Per-unit convention

Field voltage EFD is in the non-reciprocal per-unit system: $E_{F D} = 1.0$ pu produces rated terminal voltage on the air-gap line at no load. The machine's Efd input, Ifd output and Vt output use the same convention, so the exciter and machine plug together without scaling.

External voltage reference (Vref)

Enabling External Vref input exposes a Vref port that overrides the auto-initialized set-point. Because the port replaces the set-point, you must wire it when it is enabled: an unconnected Vref reads zero and collapses the reference. For a bumpless start, hold Vref at the auto-computed vref0 (shown on the Initialization tab) through $t = 0$ .

Load-flow auto-initialization

After the load flow solves, the apply pass back-calculates the set-point and the state seeds so every derivative in the diagram is zero at $t = 0$ :

Pairing is wire-traced. The initializer follows the EFD wire (through GoTo/From labels) to the unique synchronous machine whose Efd it feeds. Fan-out to several machines, or an intermediate block in the path, skips initialization with a warning.
The field voltage matches the machine. $E_{F D} (0)$ is the same $e_{f d 0}$ the machine derives from its operating point, and $V_{C} (0)$ is the terminal-voltage magnitude $V_{t}$ . At rest the machine reports $I_{f d} = E_{F D}$ .
The set-point balances the loop. With the lead-lags at DC gain 1, the rate feedback washed out and the gates idle,

V_{A} = E_{F D 0} + K_{L R} max (0, E_{F D 0} - I_{L R}), V_{ref} = V_{t} + \frac{V_{A}}{K_{A}} .

A warning is raised, and the best-effort seed still proposed, when $V_{A}$ or the voltage error falls outside its limits, when $E_{F D 0}$ lies outside $[V_{t} V_{R min}, V_{t} V_{R max} - K_{C} E_{F D 0}]$ , or when the field-current limiter is already acting at the operating point.

These quantities populate VREF, EFD(0) and VC(0) on the Initialization tab. On the first time step the model also uses $V_{C} (0)$ and $E_{F D} (0)$ in place of the not-yet-available Vt and Ifd signals, so a high-gain regulator does not kick at $t = 0$ .

Wiring

Vt ← the synchronous machine's Vt output.
EFD → the synchronous machine's Efd input.
Ifd ← the machine's field-current output (appears when KC != 0 or KLR != 0).
Optionally VS / VUEL / VOEL ← a stabilizer or limiter model, at the location chosen on the Aux Inputs tab.
Optionally Vref ← an external set-point source.

Enable Monitor EFD / VC / VA on the Monitoring tab to record the field voltage, the sensed voltage and the regulator output.

When to use something else

A rotating DC exciter: use the Type DC1A model, which has the exciter field dynamics and saturation that a static bridge lacks.
An alternator-rectifier exciter: use Type AC1A, whose rotating exciter and rectifier regulation curve set a much slower response.

Ports

Name	Direction	Value type	Notes
`Vt`	`input`	`double`
`Ifd`	`input`	`double`	Visible when `KC != 0
`Vref`	`input`	`double`	Visible when `enable_vref == 1`
`VS`	`input`	`double`	Visible when `enable_pss == 1`
`VUEL`	`input`	`double`	Visible when `enable_uel == 1`
`VOEL`	`input`	`double`	Visible when `enable_oel == 1`
`EFD`	`output`	`double`

Parameters

Regulator

Name	Label	Type	Default	Units	Description
`TR`	TR	`double`	`0.02`	`s` (`s`, `ms`)	Terminal-voltage transducer (sensing) time constant 1/(1+sTR). TR = 0 senses Vt directly.
`VIMAX`	VIMAX	`double`	`99`	—	Upper limit on the voltage error VI entering the lead-lags (pu). Usually left wide (99) so the limiter never binds.
`VIMIN`	VIMIN	`double`	`-99`	—	Lower limit on the voltage error VI entering the lead-lags (pu).
`TC`	TC	`double`	`1`	`s` (`s`, `ms`)	First lead-lag numerator (lead) time constant of (1+sTC)/(1+sTB). Set TB = TC (or both 0) to bypass; TB > TC gives transient gain reduction.
`TB`	TB	`double`	`1`	`s` (`s`, `ms`)	First lead-lag denominator (lag) time constant of (1+sTC)/(1+sTB). With TB = 0 the block is a pure lead 1+sTC (or a pass-through when TC = 0 too).
`TC1`	TC1	`double`	`0`	`s` (`s`, `ms`)	Second lead-lag numerator (lead) time constant of (1+sTC1)/(1+sTB1). TC1 > TB1 represents transient gain increase; leave both 0 to bypass.
`TB1`	TB1	`double`	`0`	`s` (`s`, `ms`)	Second lead-lag denominator (lag) time constant of (1+sTC1)/(1+sTB1).
`KA`	KA	`double`	`210`	—	Voltage-regulator gain (pu EFD per pu voltage error). Static exciters run high gain, typically 100-400.
`TA`	TA	`double`	`0`	`s` (`s`, `ms`)	Voltage-regulator time constant of the KA/(1+sTA) block. Often 0 for a thyristor bridge (the regulator responds instantly).
`VAMAX`	VAMAX	`double`	`6.43`	—	Upper non-windup limit on the regulator output VA (pu).
`VAMIN`	VAMIN	`double`	`-6`	—	Lower non-windup limit on the regulator output VA (pu).
`KF`	KF	`double`	`0`	—	Rate-feedback gain of the sKF/(1+sTF) stabilizing loop taken from EFD. Normally 0 when the lead-lag provides transient gain reduction.
`TF`	TF	`double`	`1`	`s` (`s`, `ms`)	Rate-feedback time constant. The feedback is disabled when KF = 0 or TF = 0.

Field Limits

Name	Label	Type	Default	Units	Description
`VRMAX`	VRMAX	`double`	`6.43`	—	Field-voltage ceiling factor (pu). The upper EFD limit is VtVRMAX - KCIfd: the bridge supply follows the terminal voltage.
`VRMIN`	VRMIN	`double`	`-6`	—	Field-voltage floor factor (pu). The lower EFD limit is Vt*VRMIN. Use 0 for a half-controlled bridge that cannot force negative field voltage.
`KC`	KC	`double`	`0.038`	—	Rectifier loading factor proportional to the commutating reactance. Lowers the ceiling by KC*Ifd. When KC or KLR is non-zero a field-current input Ifd appears.
`KLR`	KLR	`double`	`4.54`	—	Field-current limiter gain. Above the threshold ILR the regulator output is reduced by KLR*(Ifd - ILR). Set 0 to disable, and do so when an explicit OEL model is wired.
`ILR`	ILR	`double`	`4.4`	—	Field-current limiter threshold (pu field current).

Aux Inputs

Name	Label	Type	Default	Units	Description
`enable_vref`	External Vref input (Vref)	enum (`Off` / `On`)	`0`	—	Expose an external voltage-reference input port Vref. When on, a Vref port appears and OVERRIDES (replaces) the regulator setpoint: the wired signal is used as VREF instead of the internal, auto-initialized vref0. You must wire it - an enabled but unconnected Vref reads 0 and collapses the reference. Leave off to use the auto-computed vref0.
`enable_pss`	PSS input (VS)	enum (`Off` / `On`)	`0`	—	Expose the stabilizer input VS for a power system stabilizer. Where it enters is set by PSS location.
`pss_location`	PSS location	enum (`Voltage error (a)` / `Regulator output (b)`)	`1`	—	Where VS enters: at the voltage-error summing junction (a), or summed at the regulator output (b). Same numbering as the ESST1A VOS code.
`enable_uel`	UEL input (VUEL)	enum (`Off` / `On`)	`0`	—	Expose the under-excitation limiter input VUEL. Where it enters is set by UEL location.
`uel_location`	UEL location	enum (`Summation at voltage error (a)` / `Take-over at voltage error (b)` / `Take-over at regulator output (c)`)	`1`	—	Where VUEL enters: added at the voltage-error junction (a), through an HV (take-over) gate on the voltage error (b), or through an HV gate on the regulator output (c). Same numbering as the ESST1A UEL code.
`enable_oel`	OEL input (VOEL)	enum (`Off` / `On`)	`0`	—	Expose the over-excitation limiter input VOEL. Where it enters is set by OEL location.
`oel_location`	OEL location	enum (`Summation at voltage error (a)` / `Take-over at voltage error (b)` / `Take-over at regulator output (c)`)	`3`	—	Where VOEL enters: added at the voltage-error junction (a), through an LV (take-over) gate on the voltage error (b), or through an LV gate on the regulator output (c). ST1A has only location (c); (a) and (b) are the ST1C additions.

Monitoring

Name	Label	Type	Default	Units	Description
`measure_efd`	Monitor EFD	enum (`Off` / `On`)	`0`	—	Record the field voltage EFD (pu) as a named observable.
`measure_vc`	Monitor VC	enum (`Off` / `On`)	`0`	—	Record the sensed (transduced) terminal voltage VC (pu) as a named observable.
`measure_va`	Monitor VA	enum (`Off` / `On`)	`0`	—	Record the regulator output VA (pu, after its [VAMIN, VAMAX] limit) as a named observable.

Signal Names

Name	Label	Type	Default	Units	Description
`efd_name`	EFD name	`string`	(empty)	—	Observable name for the field voltage EFD. Blank = skip.
`vc_name`	VC name	`string`	(empty)	—	Observable name for the sensed terminal voltage VC. Blank = skip.
`va_name`	VA name	`string`	(empty)	—	Observable name for the regulator output VA. Blank = skip.

Initialization

Name	Label	Type	Default	Units	Description
`vref0`	VREF	`double`	`1`	—	Voltage-regulator setpoint reference (pu). Normally computed by the load-flow auto-initialization so the regulator starts in balance; set manually only for standalone use. Ignored at run time when the external Vref input is enabled and wired (the port overrides it).
`efd_init`	EFD(0)	`double`	`1`	—	Initial field voltage EFD at t = 0 (pu, non-reciprocal: 1.0 produces rated terminal voltage at no load). Seeds the regulator and rate-feedback states, and stands in for the field current on the first step (IFD0 = EFD0). Normally set by the load-flow auto-initialization.
`vc_init`	VC(0)	`double`	`1`	—	Initial sensed terminal voltage at t = 0 (pu). Seeds the transducer state and stands in for Vt on the first step. Normally set by the load-flow auto-initialization to the machine terminal-voltage magnitude.

Observables

Signal	Type	Default name	Enable	Description
`EFD`	`signal`	from `efd_name`	`measure_efd`	Field voltage EFD (pu, non-reciprocal) commanded to the machine's Efd input, after the [VtVRMIN, VtVRMAX - KC*Ifd] limit.
`vc`	`signal`	from `vc_name`	`measure_vc`	Sensed (transduced) terminal voltage VC (pu) after the 1/(1+sTR) transducer.
`va`	`signal`	from `va_name`	`measure_va`	Regulator output VA (pu) after its [VAMIN, VAMAX] limit, before the field-current limiter and the output gates.

Excitation System (ST1A) ​

Overview ​

Block diagram ​

Field-voltage limits and the field-current input ​

Alternate input locations ​

Per-unit convention ​

External voltage reference (Vref) ​

Load-flow auto-initialization ​

Wiring ​

When to use something else ​

Ports ​

Parameters ​

Regulator ​

Field Limits ​

Aux Inputs ​

Monitoring ​

Signal Names ​

Initialization ​

Observables ​

Used in samples ​